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final publication# 16736 rev: g amendment/ +2 issue date: march 1998 am29F010 1 megabit (128 k x 8-bit) cmos 5.0 volt-only, uniform sector flash memory distinctive characteristics n single power supply operation 5.0 v 10% for read, erase, and program operations simplifies system-level power requirements n high performance 45 ns maximum access time n low power consumption 30 ma max active read current 50 ma max program/erase current <25 m a typical standby current n flexible sector architecture eight uniform sectors any combination of sectors can be erased supports full chip erase n sector protection hardware-based feature that disables/re- enables program and erase operations in any combination of sectors sector protection/unprotection can be implemented using standard prom programming equipment n embedded algorithms embedded erase algorithm automatically pre-programs and erases the chip or any combination of designated sector embedded program algorithm automatically programs and verifies data at specified address n minimum 100,000 program/erase cycles guaranteed n package options 32-pin plcc 32-pin tsop 32-pin pdip n compatible with jedec standards pinout and software compatible with single-power-supply flash superior inadvertent write protection n data# polling and toggle bits provides a software method of detecting program or erase cycle completion
2 am29F010 general description the am29F010 is a 1 mbit, 5.0 volt-only flash memory organized as 131,072 bytes. the am29F010 is offered in 32-pin plcc, tsop, and pdip packages. the byte- wide data appears on dq0-dq7. the device is de- signed to be programmed in-system with the standard system 5.0 volt v cc supply. a 12.0 volt v pp is not re- quired for program or erase operations. the device can also be programmed or erased in standard eprom programmers. the standard device offers access times of 45, 55, 70, 90, and 120 ns, allowing high-speed microprocessors to operate without wait states. to eliminate bus con- tention the device has separate chip enable (ce#), write enable (we#) and output enable (oe) controls. the device requires only a single 5.0 volt power sup- ply for both read and write functions. internally gener- ated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single-power-supply flash standard . com- mands are written to the command register using stan- dard microprocessor write timings. register contents serve as input to an internal state machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the pro- gramming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this invokes the embedded program algorithman internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. device erasure occurs by executing the erase com- mand sequence. this invokes the embedded erase algorithman internal algorithm that automatically pre- programs the array (if it is not already programmed) be- fore executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether a program or erase operation is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is erased when shipped from the factory. the hardware data protection measures include a low v cc detector automatically inhibits write operations during power transitions. the hardware sector pro- tection feature disables both program and erase oper- ations in any combination of the sectors of memory, and is implemented using standard eprom program- mers. the system can place the device into the standby mode . power consumption is greatly reduced in this mode. amds flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the bytes are programmed one byte at a time using the eprom programming mechanism of hot electron injection.
am29F010 3 product selector guide note: see the ac characteristics section for full specifications. block diagram family part number am29F010 speed option v cc = 5.0 v 5% -45 -55 (p) v cc = 5.0 v 10% -55 (j, e, f) -70 -90 -120 max access time (ns) 45 55 70 90 120 ce# access (ns) 45 55 70 90 120 oe# access (ns) 25 30 30 35 50 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# ce# oe# stb stb dq0 C dq7 data latch y-gating cell matrix 16736g-1 address latch a0Ca16
4 am29F010 connection diagrams 16736g-2 3 4 5 2 1 9 10 11 12 13 27 26 25 24 23 7 8 22 21 6 32 31 20 14 30 29 28 15 16 19 18 17 a6 a5 a4 a3 a2 a1 a0 a16 dq0 a15 a12 a7 dq1 dq2 v ss a8 a9 a11 oe# a10 ce# dq7 v cc we# dq6 nc a14 a13 dq5 dq4 dq3 nc pdip dq6 nc dq5 dq4 dq3 1 31 30 2 3 4 5 6 7 8 9 10 11 12 13 17 18 19 20 16 15 14 29 28 27 26 25 24 23 22 21 32 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a12 a15 a16 v cc we# nc dq1 dq2 v ss plcc 16736g-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 standard tsop 16736g-4 a11 a9 a8 a13 a14 nc we# v cc nc a16 a15 a12 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a 3 16736g-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 a14 nc we# v cc nc a16 a15 a12 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a 3 reverse tsop
am29F010 5 pin configuration a0Ca16 = 17 addresses dq0Cdq7 = 8 data inputs/outputs ce# = chip enable oe# = output enable we# = write enable v cc = +5.0 volt single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = pin not connected internally logic symbol 17 8 dq0Cdq7 a0Ca16 ce# oe# we# 16736g-6
6 am29F010 ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. device number/description am29F010 1 megabit (128 k x 8-bit) cmos flash memory 5.0 volt-only read, program, and erase am29F010 -70 e c optional processing blank = standard processing b = burn-in (contact an amd representative for more information.) temperature range c = commercial (0 c to +70 c) i= industrial (C40 c to +85 c) e = extended (C55 c to +125 c) package type p = 32-pin plastic dip (pd 032) j = 32-pin rectangular plastic leaded chip carrier (pl 032) e = 32-pin thin small outline package (tsop) standard pinout (ts 032) f = 32-pin thin small outline package (tsop) reverse pinout (tsr032) speed option see product selector guide and valid combinations b valid combinations am29F010-45 pc, pi, pe, jc, ji, je, ec, ei, ee, fc, fi, fe am29F010-55 v cc = 5.0 v 5% pc5, pi5, pe5 am29F010-55 v cc = 5.0 v 10% jc, ji, je, ec, ei, ee, fc, fi, fe am29F010-70 am29F010-90 am29F010-120 pc, pi, pe, jc, ji, je, ec, ei, ee, fc, fi, fe
am29F010 7 device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is composed of latches that store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the appropriate device bus operations table lists the inputs and control levels required, and the re- sulting output. the following subsections describe each of these operations in further detail. table 1. am29F010 device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5 v, x = dont care, a in = addresses in, d in = data in, d out = data out notes: 1. addresses are a16:a0. 2. the sector protect and sector unprotect functions must be implemented via programming equipment. see the sector pro- tection/unprotection section. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should re- main at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware re- set. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see reading array data for more information. refer to the ac read operations table for timing specifica- tions and to the read operations timings diagram for the timing waveforms. i cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . an erase operation can erase one sector, multiple sec- tors, or the entire device. the sector address tables indicate the address space that each sector occupies. a sector address consists of the address bits required to uniquely select a sector. see the command defini- tions section for details on erasing a sector or the en- tire chip. after the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7Cdq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence sections for more information. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. operation ce# oe# we# addresses (note 1) dq0Cdq7 read l l h a in d out write l h l a in d in standby v cc 0.5 v x x x high-z output disable l h h x high-z hardware reset x x x x high-z temporary sector unprotect x x x a in d in
8 am29F010 program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on dq7Cdq0. standard read cycle timings and i cc read specifications apply. refer to write operation status for more information, and to each ac charac- teristics section in the appropriate data sheet for timing diagrams. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the oe# input. the device enters the cmos standby mode when the ce# pin is held at v cc 0.5 v. (note that this is a more restricted voltage range than v ih .) the device enters the ttl standby mode when ce# is held at v ih . the device requires the standard access time (t ce ) before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in the dc characteristics tables represents the standby current specification. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high imped- ance state. table 2. am29F010 sector addresses table autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7Cdq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in autoselect codes (high voltage method) table. in ad- dition, when verifying sector protection, the sector ad- dress must appear on the appropriate highest order address bits. refer to the corresponding sector ad- dress tables. the command definitions table shows the remaining address bits that are dont care. when all necessary bits have been set as required, the program- ming equipment may then read the corresponding identifier code on dq7Cdq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the command defini- tions table. this method does not require v id . see command definitions for details on using the autose- lect mode. sector a16 a15 a14 address range sa0 0 0 0 00000h-03fffh sa1 0 0 1 04000h-07fffh sa2 0 1 0 08000h-0bfffh sa3 0 1 1 0c000h-0ffffh sa4 1 0 0 10000h-13fffh sa5 1 0 1 14000h-17fffh sa6 1 1 0 18000h-1bfffh sa7 1 1 1 1c000h-1ffffh
am29F010 9 table 3. am29F010 autoselect codes (high voltage method) l = logic low = v il , h = logic high = v ih , sa = sector address, x = dont care. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously pro- tected sectors. sector protection/unprotection must be implemented using programming equipment. the procedure re- quires a high voltage (v id ) on address pin a9 and the control pins. details on this method are provided in a supplement, publication number 20495. contact an amd representative to obtain a copy of the appropriate document. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amds expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is protected or unprotected. see autoselect mode for details. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the command defi- nitions table). in addition, the following hardware data protection measures prevent accidental erasure or pro- gramming, which might otherwise be caused by spuri- ous system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent uninten- tional writes when v cc is greater than v lko . write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cy- cle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to reading array data on power-up. description ce# oe# we# a16 to a14 a13 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq7 to dq0 manufacturer id : amd l l h x x v id xlxll 01h device id: am29F010 l l h x x v id xlxlh 20h sector protection verification l l h sa x v id xlxhl 01h (protected) 00h (unprotected)
10 am29F010 command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. the command definitions table defines the valid register command sequences. writing incorrect address and data values or writing them in the im- proper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appropriate timing diagrams in the ac characteristics section. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or em- bedded erase algorithm. the system must issue the reset command to re-en- able the device for reading array data if dq5 goes high, or while in the autoselect mode. see the reset com- mand section, next. see also requirements for reading array data in the device bus operations section for more information. the read operations table provides the read parame- ters, and read operation timings diagram shows the timing diagram. reset command writing the reset command to the device resets the de- vice to reading array data. address bits are dont care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence be- fore programming begins. this resets the device to reading array data. once programming begins, how- ever, the device ignores reset commands until the op- eration is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data. if dq5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data. autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. this method is an alternative to that shown in the autoselect codes (high voltage method) table, which is intended for prom program- mers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h or retrieves the manu- facturer code. a read cycle at address xx01h returns the device code. a read cycle containing a sector ad- dress (sa) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. refer to the sector address tables for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. byte program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two un- lock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verify the pro- grammed cell margin. the command definitions take shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7or dq6. see write operation status for informa- tion on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a 0 back to a 1. attempting to do so may halt the operation and set dq5 to 1, or cause the data# polling algorithm to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still 0. only erase operations can convert a 0 to a 1.
am29F010 11 note: see the appropriate command definitions table for program command sequence. figure 1. program operation chip erase command sequence chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. the command definitions table shows the address and data require- ments for the chip erase command sequence. any commands written to the chip during the embed- ded erase algorithm are ignored. the system can determine the status of the erase operation by using dq7 or dq6. see write opera- tion status for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and ad- dresses are no longer latched. figure 2 illustrates the algorithm for the erase opera- tion. see the erase/program operations tables in ac characteristics for parameters, and to the chip/sector erase operation timings for timing waveforms. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock write cycles are then followed by the ad- dress of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 m s begins. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time be- tween these additional cycles must be less than 50 m s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress 16736g-7
12 am29F010 written. if the time between additional sector erase commands can be assumed to be less than 50 m s, the system need not monitor dq3. any command during the time-out period resets the device to reading array data. the system must rewrite the command se- quence and any additional sector addresses and com- mands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see the dq3: sector erase timer section.) the time-out begins from the ris- ing edge of the final we# pulse in the command se- quence. once the sector erase operation has begun, all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the sta- tus of the erase operation by using dq7 or dq6. refer to write operation status for information on these status bits. figure 2 illustrates the algorithm for the erase opera- tion. refer to the erase/program operations tables in the ac characteristics section for parameters, and to the sector erase operations timing diagram for timing waveforms. notes: 1. see the appropriate command definitions table for erase command sequence. 2. see dq3: sector erase timer for more information. figure 2. erase operation start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress 16736g-8
am29F010 13 table 4. am2f010 command definitions legend: x = dont care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a16Ca14 uniquely select any sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all command bus cycles are write operations. 4. no unlock or command cycles required when reading array data. 5. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 6. the fourth cycle of the autoselect command sequence is a read operation. 7. the data is 00h for an unprotected sector and 01h for a protected sector. see autoselect command sequence for more information. command sequence (note 1) bus cycles (notes 2-3) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 4) 1 ra rd reset (note 5) 1 xxxx f0 autoselect (note 6) manufacturer id 4 5555 aa 2aaa 55 5555 90 xx00 01 device id 4 5555 aa 2aaa 55 5555 90 xx01 20 sector protect verify (note 7) 4 5555 aa 2aaa 55 5555 90 (sa) x02 00 01 program 4 5555 aa 2aaa 55 5555 a0 pa pd chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa 30 cycles
14 am29F010 write operation status the device provides several bits to determine the sta- tus of a write operation: dq3, dq5, dq6, and dq7. table 5 and the following subsections describe the functions of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or completed. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. when the embedded program algo- rithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sec- tor, data# polling on dq7 is active for approximately 2 m s, then the device returns to reading array data. during the embedded erase algorithm, data# polling produces a 0 on dq7. when the embedded erase al- gorithm is complete, data# polling produces a 1 on dq7. this is analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. the system must provide an address within any of the sectors selected for erasure to read valid status in- formation on dq7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data# polling on dq7 is active for approximately 100 m s, then the de- vice returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7C dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0Cdq6 while output enable (oe#) is asserted low. the data# poll- ing timings (during embedded algorithms) figure in the ac characteristics section illustrates this. table 5 shows the outputs for data# polling on dq7. figure 3 shows the data# polling algorithm. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7Cdq0 addr = va read dq7Cdq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 16736g-9 figure 3. data# polling algorithm
am29F010 15 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the com- mand sequence (prior to the program or erase opera- tion), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycles.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 100 m s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. if a program address falls within a protected sector, dq6 toggles for approximately 2 m s after the program command sequence is written, then returns to reading array data. the write operation status table shows the outputs for toggle bit i on dq6. refer to figure 4 for the toggle bit algorithm, and to the toggle bit timings figure in the ac characteristics section for the timing diagram. reading toggle bit dq6 refer to figure 4 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7Cdq0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the sys- tem would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7Cdq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog- gling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, de- termining the status as described in the previous para- graph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 4). start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7Cdq0 toggle bit = toggle? read dq7Cdq0 twice read dq7Cdq0 notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1. see text. 16736g-10 figure 4. toggle bit algorithm (notes 1, 2) 1
16 am29F010 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1. this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a 1. under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if addi- tional sectors are selected for erasure, the entire time- out also applies after each additional sector erase command. when the time-out is complete, dq3 switches from 0 to 1. the system may ignore dq3 if the system can guarantee that the time between ad- ditional sector erase commands will always be less than 50 m s. see also the sector erase command se- quence section. after the sector erase command sequence is written, the system should read the status on dq7 (data# poll- ing) or dq6 (toggle bit i) to ensure the device has ac- cepted the command sequence, and then read dq3. if dq3 is 1, the internally controlled erase cycle has be- gun; all further commands are ignored until the erase operation is complete. if dq3 is 0, the device will ac- cept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 5 shows the out- puts for dq3. table 5. write operation status notes: 1. dq7 requires a valid address when reading status information. refer to the appropriate subsection for further details. 2. dq5 switches to 1 when an embedded program or embedded erase operation has exceeded the maximum timing limits. see dq5: exceeded timing limits for more information. operation dq7 (note 1) dq6 dq5 (note 2) dq3 embedded program algorithm dq7# toggle 0 n/a embedded erase algorithm 0 toggle 0 1
am29F010 17 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . C65 c to +125 c ambient temperature with power applied . . . . . . . . . . . . . C55 c to +125 c voltage with respect to ground v cc (note 1). . . . . . . . . . . . . . . . . . . . C2.0 v to +7.0 v a9 (note 2). . . . . . . . . . . . . . . . . . . .C2.0 v to +12.5 v all other pins (note 1) . . . . . . . . . . . .C2.0 v to +7.0 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pin is C0.5 v. during voltage transitions, inputs may overshoot v ss to C2.0 v for periods of up to 20 ns. see figure 5. maximum dc voltage on input and i/o pins is v cc + 0.5 v. during volt- age transitions, input and i/o pins may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 6. 2. minimum dc input voltage on a9 pin is C0.5v. during voltage transitions, a9 pins may overshoot v ss to C2.0 v for periods of up to 20 ns. see figure 5. maximum dc in- put voltage on a9 is +12.5 v which may overshoot to 13.5 v for periods up to 20 ns. 3. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the op- erational sections of this specification is not implied. expo- sure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 5. maximum negative overshoot waveform figure 6. maximum positive overshoot waveform operating ranges commercial (c) devices case temperature (t a ) . . . . . . . . . . . . . 0 c to +70 c industrial (i) devices case temperature (t a ) . . . . . . . . . . . C40 c to +85 c extended (e) devices case temperature (t a ) . . . . . . . . . . C55 c to +125 c v cc supply voltages v cc for 5% devices . . . . . . . . . . .+4.75 v to +5.25 v v cc for 10% devices . . . . . . . . . .+4.50 v to +5.50 v operating ranges define those limits between which the functionality of the device is guaranteed. 20 ns 20 ns +0.8 v C0.5 v 20 ns C2.0 v 16736g-11 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v 16736g-12
18 am29F010 dc characteristics ttl/nmos compatible notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. i cc active while embedded program or embedded erase algorithm is in progress. 3. not 100% tested. parameter symbol parameter description test description min max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 m a i lit a9 input load current v cc = v cc max, a9 = 12.5 v 50 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 m a i cc1 v cc active current (note 1) ce# = v il, oe# = v ih, v cc = v cc max 30 ma i cc2 v cc active current (notes 2, 3) ce# = v il, oe# = v ih, v cc = v cc max 50 ma i cc3 v cc standby current v cc = v cc max, ce# and oe# = v ih 1.0 ma v il input low voltage C0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v id voltage for autoselect and temporary sector unprotect v cc = 5.0 v 11.5 12.5 v v ol output low voltage i ol = 12 ma, v cc = v cc min 0.45 v v oh output high voltage i oh = C2.5 ma, v cc = v cc min 2.4 v v lko low v cc lock-out voltage 3.2 4.2 v
am29F010 19 dc characteristics (continued) cmos compatible notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. i cc active while embedded program or embedded erase algorithm is in progress. 3. not 100% tested. parameter symbol parameter description test description min max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 m a i lit a9 input load current v cc = v cc max, a9 = 12.5 v 50 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 m a i cc1 v cc active current (note 1) ce# = v il, oe# = v ih, v cc = v cc max 30 ma i cc2 v cc active current (notes 2, 3) ce# = v il, oe# = v ih, v cc = v cc max 50 ma i cc3 v cc standby current v cc = v cc max, ce# = v cc 0.5 v, oe# = v ih 100 m a v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.5 v v id voltage for autoselect and temporary sector unprotect v cc = 5.0 v 11.5 12.5 v v ol output low voltage i ol = 12 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = C2.5 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = C100 m a, v cc = v cc min v cc C0.4 v v lko low v cc lock-out voltage 3.2 4.2 v
20 am29F010 test conditions table 6. test specifications key to switching waveforms 2.7 k w c l 6.2 k w 5.0 v device under te s t 16736g-13 figure 7. test setup note: diodes are in3064 or equivalent test condition -45 all others unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 20 ns input pulse levels 0.0C3.0 0.45C2.4 v input timing measurement reference levels 1.5 0.8 v output timing measurement reference levels 1.5 2.0 v ks000010-pal waveform inputs outputs steady changing from h to l changing from l to h dont care, any change permitted changing, state unknown does not apply center line is high impedance state (high z)
am29F010 21 ac characteristics read-only operations characteristics notes: 1. not 100% tested. 2. output driver disable time. 3. see figure 7 and table 6 for test specifications. parameter symbol parameter description test setup -45 -55 -70 -90 -120 unit jedec std. t avav t rc read cycle time (note 1) min 45 55 70 90 120 ns t avqv t acc address to output delay ce# = v il oe# = v il max 45 55 70 90 120 ns t elqv t ce chip enable to output delay oe# = v il max 45 55 70 90 120 ns t glqv t oe output enable to output delay max 25 30 30 35 50 ns t ehqz t df chip enable to output high z (notes 1, 2) max 10 15 20 20 30 ns t ghqz t df output enable to output high z (notes 1, 2) max 10 15 20 20 30 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data polling min 10 ns t axqx t oh output hold time from addresses ce# or oe#, whichever occurs first min 0 ns t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe t df t oh 16736g-14 figure 8. read operations timings
22 am29F010 ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the erase and programming performance section for more informaiton. parameter symbol parameter description -45 -55 -70 -90 -120 unit jedec standard t avav t wc write cycle time (note 1) min 45 55 70 90 120 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 35 45 45 45 50 ns t dvwh t ds data setup time min 20 20 30 45 50 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recover time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 25 30 35 45 50 ns t whwl t wph write pulse width high min 20 ns t whwh1 t whwh1 byte programming operation (note 2) typ 14 m s t whwh2 t whwh2 sector erase operation (note 2) typ 1.0 sec t vcs v cc set up time (note 1) min 50 m s
am29F010 23 ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t ghwl t cs status d out program command sequence (last two cycles) t ch pa note: pa = program address, pd = program data, d out is the true data at the program address. figure 9. program operation timings 16736g-13 oe# ce# addresses v cc we# data 2aah sa t ghwl t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data note: sa = sector address (for sector erase), va = valid address for reading status data (see write operation status). figure 10. chip/sector erase operation timings 16736g-13
24 am29F010 ac characteristics we# ce# oe# high z t oe high z dq7 dq0Cdq6 complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 16736g-15 figure 11. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe dq6 addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 16736g-16 figure 12. toggle bit timings (during embedded algorithms)
am29F010 25 ac characteristics erase and program operations alternate ce# controlled writes notes: 1. not 100% tested. 2. see the erase and programming performance section for more information. parameter symbol parameter description -45 -55 -70 -90 -120 unit jedec standard t avav t wc write cycle time (note 1) min 45 55 70 90 120 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 35 45 45 45 50 ns t dveh t ds data setup time min 20 20 30 45 50 ns t ehdx t dh data hold time min 0 ns t oes output enable setup time (note 1) min 0 ns t ghel t ghel read recover time before write min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 25 30 35 45 50 ns t ehel t cph ce# pulse width high min 20 ns t whwh1 t whwh1 byte programming operation (note 2) typ 14 m s t whwh2 t whwh2 chip/sector erase operation (note 2) typ 1.0 sec
26 am29F010 ac characteristics erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 5.0 v v cc , 100,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 4.5 v (4.75 v for -45, -55 pdip), 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. if the maximum byte program time given is exceeded, only then does the device set dq5 = 1. see the section on dq5 for further information. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the four-bus-cycle command sequence for programming. see table 1 for further information on command definitions. 6. the device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaranteed. t ghel t ws oe# ce# we# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t whwh1 or 2 t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase notes: 1. pa = program address, pd = program data, sa = sector address, dq7# = complement of data input, d out = array data. 2. figure indicates the last two bus cycles of the command sequence. 16736g-17 figure 13. alternate ce# controlled write operation timings parameter limits comments typ (note 1) max (note 2) unit chip/sector erase time 1.0 15 sec excludes 00h programming prior to erasure (note 4) byte programming time 14 1000 m s excludes system-level overhead (note 5) chip programming time (note 3) 1.8 12.5 sec
am29F010 27 latchup characteristic note: includes all pins except v cc . test conditions: v cc = 5.0 volt, one pin at a time. tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. plcc and pdip pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. data retention parameter description min max input voltage with respect to v ss on i/o pins C1.0 v v cc + 1.0 v v cc current C100 ma +100 ma parameter symbol parameter description test conditions typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 8 10 pf parameter symbol parameter description test conditions typ max unit c in input capacitance v in = 0 4 6 pf c out output capacitance v out = 0 8 12 pf c in2 control pin capacitance v pp = 0 8 12 pf parameter description test conditions min unit minimum pattern data retention time 150 c 10 years 125 c 20 years
28 am29F010 physical dimensions pd 032 32-pin plastic dip (measured in inches) pl 032 32-pin plastic leaded chip carrier (measured in inches) pin 1 i.d. 1.640 1.680 .530 .580 .005 min .045 .065 .090 .110 .140 .225 .120 .160 .014 .022 seating plane .015 .060 16-038-sb_ag pd 032 dg75 2-28-95 ae 32 17 16 .630 .700 0? 10? .600 .625 .008 .015 .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530
am29F010 29 physical dimensions (continued) ts 032 32-pin standard thin small outline package (measured in millimeters) pin 1 i.d. 1 18.30 18.50 7.90 8.10 0.50 bsc 0.05 0.15 0.95 1.05 16-038-tsop-2 ts 032 da95 4-4-95 ae 19.80 20.20 1.20 max 0.50 0.70 0.10 0.21 0.25mm (0.0098") bsc 0 5 0.08 0.20
30 am29F010 physical dimensions (continued) tsr 032 32-pin standard thin small outline package (measured in millimeters) 1 18.30 18.50 19.80 20.20 7.90 8.10 0.50 bsc 0.05 0.15 0.95 1.05 16-038-tsop-2 tsr032 da95 4-4-95 ae pin 1 i.d. 1.20 max 0.50 0.70 0.10 0.21 0.25mm (0.0098") bsc 0 5 0.08 0.20
am29F010 31 revision summary for am29F010 revision f+1 product selector guide there are now two v cc supply operating ranges avail- able for the 55 ns speed option. the pdip package is only available in the 5% v cc operating range. the other packages are available in the 10% operating range. ordering information the 45 ns speed grade is now also available in pc con- figuration (pdip package, commercial temperature.) operating ranges v cc supply voltages: changed to reflect the available speed options. ac characteristics write/erase/program operations: corrected to indicate t vlht , t oesp , t whwh1 , and t whwh2 are typical values, not minimum values. changed value for t whwh2 . ac characteristics write/erase/program operations, alternate ce# con- trolled writes: corrected to indicate t whwh1 and t whwh2 are typical values, not minimum values. changed value for t whwh2 . erase and programming performance combined chip and sector erase specifications; changed typical and maximum values. added note 6. revision g global made formatting and layout consistent with other data sheets. used updated common tables and diagrams. revision g+1 table 4, command definitions address bits a0Ca14 are required for unlock cycles. therefore, addresses for second and fifth write cycles are 2aaah. addresses for first, third, fourth, and sixth cycles are 5555h. read cycles are not affected. de- leted note 4 to reflect the correction. revision g+2 ac characteristics erase/program operations; erase and program oper- ations alternate ce# controlled writes: corrected the notes reference for t whwh1 and t whwh2 . these param- eters are 100% tested. corrected the note reference for t vcs . this parameter is not 100% tested. trademarks copyright ? 1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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